Numerous devices have been developed for handling electrostatic discharge (ESD) events. These ESD protection devices may be categorized as falling into two groups: the active devices that work in normal operating mode, and the snapback devices which are designed to be triggered and operate in snapback mode during an ESD event and then turn off again as voltage drops below the holding voltage of the device.
NLDMOS and DMOS devices are intended to be used in normal mode and will be destroyed if they go into snapback. Even high voltage NLDMOS and DMOS devices will only survive if the voltage they are handling does not exceed the capabilities of the device. While these devices typically are meant not to go into snapback, local overstresses due to current crowding can cause these devices to go into snapback, thereby damaging the device. Thus, in the case of an ESD event, unless the device is made extremely large, the device is pushed past its capabilities and goes into snapback, causing irreversible breakdown. Typically the margin is rather small before the devices go into snapback. This problem is exacerbated by the fact that the snapback voltage is dependent on gate bias and in practice high-voltage devices used for voltage regulation to provide a low voltage to internal circuits are often not directly connected to the power pad and ground. Thus they fail to provide local clamping of the high voltage pad and ground.
A typical NLDMOS, more correctly referred to as a drain extended MOS (DeMOS) is shown in cross-section in FIG. 1, which includes an n-epitaxial layer 100 in which an n-well 102 is formed. In the case of a BiCMOS process an n-buried layer (NBL) 103 may also be formed in the n-epi 100. An n+ drain 104 is formed in the n-well 102, and an n+ source 106 is formed in a p-well 108 in the n-epi 100. A polysilicon gate 110 is formed on top of the n− and p-wells 102, 108, the extended portion of the gate 110 being isolated from the n-well 102 by an isolation oxide 112. As shown in FIG. 1, the drain 104 includes a drain contact 114, the source 106 includes a source contact 116, and the gate 110 includes a gate contact 120.
FIG. 2 shows another prior art device in cross-section, namely an NLDMOS-SCR, which is capable of operating in snapback mode but suffers from considerable on-state resistance losses during normal mode. This device includes an n-epitaxial layer 200 grown on a p-substrate 201. An n-well 202 is formed in the n-epi 200. In the case of a BiCMOS process an n-buried layer (NBL) 203 may also be formed in the n-epi 200. In the n-epitaxial layer 200, an n+ drain 204 is formed, and an n+ source 206 is formed in a p-well 208 in the n-epi 200. A polysilicon gate 210 is formed on top of the n- and p-wells 202, 208, the extended portion of the gate 210 being isolated from the n-well 202 by an isolation oxide 212. As shown in FIG. 2, the drain 204 includes a drain contact 214, the source includes a source contact 216, and the gate 210 includes a gate contact 220. Unlike the NLDMOS of FIG. 1, this NLDMOS-SCR further includes a p-emitter region 222 formed under the drain contact. This device functions well insofar as it moves the hot spot (shown by region 130) away from the drain contact 214. However, the inclusion of the p-emitter region 222 introduces additional process steps that are typically not required for the devices it supports. Also, the inclusion of the p-emitter region 222 results in a significant saturation NWELL resistor. Thus, the device on-state current is rather low since only the bottom portion of the NWELL under the p-emitter 222 can conduct the current.
The present invention seeks to provide an alternative solution for devices that will not only operate well during normal mode but are also capable of surviving a snapback scenario.